Novas Announces Industry's First Unified Design, Assertion And Testbench Debug SolutionDebug leader adds comprehensive verification language support, Integrates analysis of design, assertion and testbench interaction
SAN JOSE, Calif., February 16, 2004 — Novas Software, Inc., the leader in debug systems for complex chip designs, today announced a breakthrough in Verification Process Automation (VPA) that allows engineers to debug automated testbench code, assertions, and Verilog and VHDL designs all within a single environment. For the first time, engineers can debug across language boundaries that until now have separated the verification language source code used to create testbench programs from the hardware design language (HDL) code used to describe chip designs. By applying powerful debug capabilities to the testbench, advanced verification environments and assertion domains, engineers can analyze and better understand the behavior of complex verification structures for faster overall debug.
Novas is delivering the new nBenchTM capability as an integral component of its core debug platform with the VerdiTM Behavior-Based and Debussy® Debug Systems. nBench applies advanced debug features, including language tracing, event analysis and active annotation, to testbench debug in a manner consistent with design debug. The result is a complete verification solution that allows for a more effective, unified approach to design and testbench analysis.
nBench supports Verisity’s VPA solutions including the emerging IEEE P1647 standard for the e functional verification language, in addition to the Vera® testbench automation tool within the Synopsys Discovery™ Verification Platform. This augments Novas’ existing support of the OpenVera Assertions (OVA) and Accellera SystemVerilog languages, and forthcoming support for Accellera’s Property Specification Language (PSL) standard.
“The use of different languages by multiple teams for design, testbench and assertions leads to a disconnected verification process and complicated debug scenarios,”
said Dave Kelf, vice president of marketing at Novas. “We’re bringing automated verification environments, testbench automation and advanced design and assertion-driven debug together for the first time in a unified flow. This dramatically improves the ability of engineers to comprehend testbench behavior inline with design and assertion code, trace the root cause of problems across design and verification models, and track issues faster and more efficiently.”
Integrated Testbench Debug
Building tests that discover whether there are functional errors in an integrated circuit or system-on-chip device has become at least as difficult as designing the chip itself. With testbench creation now a fundamental part of the design process, it can typically comprise greater than half the source code of a chip design/verification project. Design teams are already spending 70 percent or more of their engineering effort on verification, and an error in the testbench is both time consuming to track down and often less obvious than a design problem. As a result, there is an urgent need for automated testbench debug processes and design-for-verification tool flow integrations.
Novas’ nBench provides a graphical way for engineers to visualize, analyze and act upon the results of their testbench verification efforts. They can browse the source code of testbench programs, examine and annotate event information onto the testbench structure, and seamlessly traverse between design and verification code across block, chip and system hierarchies.
Future testbench debug enhancements will extend database support to more complex object-oriented source code and higher-level transactions, and extend interoperability with third-party testbench automation systems to include interactive methods.
Verification Process Automation
Novas’ nBench is also a key component of the VPA initiative established by Novas, Verisity and 0-In Design Automation that combines well-defined processes, technology and methodology to simplify verification. nBench’s support for the e language is part of the total VPA solution that integrates Novas’ debug systems, Verisity’s spec-driven verification management, and 0-In’s assertion and formal verification capabilities.
“SoC verification requires billions of verification cycles, management of 100's of Gb’s of information, distributed compute and engineering resources, and interdependent hardware and software. VPA manages this complexity by automating the most-time consuming, error-prone verification processes. It also integrates the various stakeholders in a project team by giving each specialist the best open standard languages and analysis views for their needs,” said Steve Glaser, vice president of corporate marketing and business development at Verisity. “Novas’ nBench closes the gap between design and verification environments by integrating all required views in a single interactive environment.”
“Providing a unified debug solution that incorporates both complex verification environments and internal structural details of a design under test is a key step towards greater verification productivity,” noted Steve White, 0-In's president and CEO. “By combining testbench debug, assertions and design analysis, Novas’ nBench capability delivers on the concepts of Verification Process Automation.”
Availability & Pricing
nBench is available immediately, included at no charge with Verdi and Debussy system bundles. It can be purchased as an optional add-on for modular Debussy licenses with the U.S. list price starting at $4,000 for a one-year subscription license.
About Novas
Novas is the pioneer of debug systems that reduce functional verification costs for complex integrated circuit and system-on-chip designs. Its market-leading VerdiTM and Debussy® Debug Systems, along with the ReusnerTM Design Knowledge Publisher, go far beyond waveforms to help engineers understand and analyze complex or unfamiliar design behavior and share knowledge across global organizations. They cut by half or more the time it takes to locate, isolate and solve the root causes of design and verification problems. Novas is ranked first in customer satisfaction for the second consecutive year in a comprehensive EDA study published by CMP. There are more than 12,000 Novas systems installed worldwide by over 400 companies and 35 EDA companies utilizing Novas technology in their products today. Novas is headquartered in San Jose, Calif. with offices in Europe, Japan and Asia-Pacific. For more information, visit www.novas.com or email info@novas.com
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Debussy is a registered trademark, and nBench and Verdi are trademarks of Novas Software, Inc. All other trademarks or registered trademarks are the property of their respective owners.
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